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Chip Design Services

The engineering firms that turn a specification into a tapeout.

India’s established strength in the semiconductor chain. Design services are people-intensive rather than capital-intensive, which is why they arrived here decades before fabrication did.

What these figures mean
Import dependency
The share of Indian demand for this input that is met by imports today. A percentage is published only where we can state the basis for it, and the build rejects a figure that has none. “Not established” means no sourced figure exists yet, not that the figure is zero; for the domestic picture, read “Made in India today” instead.
Made in India today
How much of this input is actually produced in India: none, pilot scale, partial, or established. This is the field to read when import dependency is not established.
MSME entry capital
What it would plausibly cost an Indian MSME to enter this input at the smallest viable scale, in crore rupees. Plant and equipment only; it excludes working capital and the qualification cycle.
Time to qualify
How long from a working sample to a qualified first shipment, once the line exists. Qualification, not construction, is what usually decides whether an entry succeeds.
India readiness tier
Our verdict on whether an Indian founder can realistically enter this input, derived from the four figures above and stated as one of three tiers.

The three tiers

Tier A: Buildable Now
Under roughly Rs 5 crore of entry capital and 12 to 24 months to a qualified first shipment. A founder can start here.
Tier B: Partnership or Distribution
There is real money here, but not in manufacturing the thing. The opening is in stocking, distribution, purity uplift or a licensed partnership.
Tier C: Not Yet
Requires a joint venture, a technology licence, or a multinational’s balance sheet. Worth understanding, not worth starting.

Made in India today

None
No Indian production we can identify. Demand is met entirely from abroad.
Pilot scale
Made in India at laboratory, pilot-line or single-customer scale only.
Partial
Real Indian production exists, but it covers part of the range or part of the demand.
Established
Indian production is routine and qualified, at commercial volume.

8 entries

ASIC Turnkey Design Services

Firms that take a customer specification all the way to working packaged silicon, absorbing tool licences, IP procurement and foundry interface along the way.

TierA
Imported Not established
EntryRs 1.5–3 Cr
Qualify12–18 mo

Design Verification Services

Contracted verification engineering. The largest single category of semiconductor work done in India by headcount, and the usual first hire for a new design team.

TierA
Imported Not established
Entry<Rs 1.5 Cr
Qualify6–12 mo

Physical Design and Implementation Services

Floorplanning, placement, routing and timing closure delivered as a service. The most tool-dependent and most schedule-critical part of the design flow.

TierA
Imported Not established
EntryRs 1.5–3 Cr
Qualify12–18 mo

Post-Silicon Validation and Test Engineering

Bringing first silicon up on a bench, characterising it against specification, and writing the test programs the assembly line will later run in volume.

TierA
Imported Not established
EntryRs 3–5 Cr
Qualify12–18 mo

DFT Engineering Services

Contract engineering that makes a chip testable: inserting scan chains, compressing patterns and driving coverage up before the design is frozen.

TierA
Imported Not established
Entry<Rs 1.5 Cr
Qualify0–6 mo

Package Design and Signal Integrity

Designing the substrate, the routing and the power delivery around a die, and proving by simulation that the package will not degrade the signals passing through it.

TierA
Imported Not established
EntryRs 1.5–3 Cr
Qualify6–12 mo

Foundry PDK and Design Enablement

Building and validating the process design kits that let designers target a fab at all: the models, rule decks and libraries that describe what the process can do.

TierB
Imported Not established
Entry<Rs 1.5 Cr
Qualify12–18 mo

Mask Data Prep and OPC

Turning a finished layout into the data a mask writer can use, correcting for the optical distortions of the exposure and fracturing the result into writeable shapes.

TierC
Imported Not established
EntryRs 3–5 Cr
Qualify18–30 mo